CD4027BC DUAL J-K MASTER

CD4027BC DUAL J-K MASTER

Fr1,000 Fr800

Description

General Description These dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and Pchannel enhancement mode transistors. Each flip-flop has independent J, K, set, reset, and clock inputs and buffered Q and Q outputs. These flip-flops are edge sensitive to the clock input and change state on the positive-going transition of the clock pulses. Set or reset is independent of the clock and is accomplished by a high level on the respective input. All inputs are protected against damage due to static discharge by diode clamps to VDD and VSS. Features Y Wide supply voltage range 3.0V to 15V Y High noise immunity 0.45 VDD (typ.) Y Low power TTL Fan out of 2 driving 74L compatibility or 1 driving 74LS Y Low power 50 nW (typ.) Y Medium speed operation 12 MHz (typ.) with 10V supply

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